IEICE TRANSACTIONS on Electronics
A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
Summary :
A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.288-294
- Publication Date
- 2010/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.288
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
- Category
Authors
Keyword
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Koichi ONO, Takeshi OHKAWA, Masahiro SEGAMI, Masao HOTTA, "A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 288-294, March 2010, doi: 10.1587/transele.E93.C.288.
Abstract: A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.288/_p
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@ARTICLE{e93-c_3_288,
author={Koichi ONO, Takeshi OHKAWA, Masahiro SEGAMI, Masao HOTTA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique},
year={2010},
volume={E93-C},
number={3},
pages={288-294},
abstract={A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.},
keywords={},
doi={10.1587/transele.E93.C.288},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 288
EP - 294
AU - Koichi ONO
AU - Takeshi OHKAWA
AU - Masahiro SEGAMI
AU - Masao HOTTA
PY - 2010
DO - 10.1587/transele.E93.C.288
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.
ER -
English
