Possible functional roles of the phase resetting control during rhythmic movements have been attracting much attention in the field of robotics. The phase resetting control is a control mechanism in which the phase shift of periodic motion is induced depending on the timing of a given perturbation, leading to dynamical stability such as a rapid transition from an unstable state to a stable state in rhythmic movements. A phase response curve (PRC) is used to quantitatively evaluate the phase shift in the phase resetting control. It has been demonstrated that an optimal PRC for bipedal walking becomes bimodal. The PRCs acquired by reinforcement learning in simulated biped walking are qualitatively consistent with measured results obtained from experiments. In this study, we considered how such characteristics are obtained from a mathematical point of view. First, we assumed a symmetric Bonhoeffer-Van der Pol oscillator and phase excitable element known as an active rotator as a model of the central pattern generator for controlling rhythmic movements. Second, we constructed feedback control systems by combining them with manipulators. Next, we numerically computed the PRCs of such systems and compared the resulting PRCs. Furthermore, we approximately calculated analytical solutions of the PRCs. Based on the results, we systematically investigated the parameter dependence of the analytical PRCs. Finally, we investigated the requirements for realizing an optimal PRC for the phase resetting control during rhythmic movements.

In this paper, operator-based reset control for a class of nonlinear systems with unknown bounded disturbance is considered using right coprime factorization approach. In detail, firstly, for dealing with the unknown bounded disturbance of the nonlinear systems, operator-based reset control framework is proposed based on right coprime factorization. By the proposed framework, robust stability of the nonlinear systems with unknown bounded disturbance is guaranteed by using the proposed reset controller. Secondly, under the reset control framework, an optimal design scheme is discussed for minimizing the error norm based on the proposed operator-based reset controller. Finally, for conforming effectiveness of the proposed design scheme, a simulation example is given.

This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.

In resetting attacks against a proof system, a prover or a verifier is reset and enforced to use the same random tape on various inputs as many times as an adversary may want. Recent deployment of cloud computing gives these attacks a new importance. This paper shows that argument systems for any NP language that are both resettably-sound and resettable zero-knowledge are possible by a constant-round protocol in the BPK model. For that sake, we define and construct a resettably-extractable conditional commitment scheme.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (Va-bias) during the ramp-up period. It is revealed that the proper Va-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the Va-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40 ns and the address period of each subfield can be significantly reduced by about 43 µs.

This paper presents a construction of a single-event-upset (SEU) tolerant reset-set (RS) flip-flop (FF). The proposed RS-FF consists of four identical parts which form an interlocking feedback loop just like DICE. The area and average power consumption of the proposed RS-FFs are 1.101.48 and 1.201.63 times smaller than those of the conventional SEU tolerant RS-FFs, respectively.

A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

This paper proposes a new reset driving waveform to widen the driving margin under a low address voltage in AC-PDPs. The proposed reset waveform alters the wall charge distribution between the X-Y electrodes by applying an X-ramp bias prior to an address-period, thereby lowering the minimum level of the scan pulse (ΔVy) during an address-period without any misfiring discharge in the off-cells. When adopting the proposed reset waveform, the address discharge time delay is reduced by about 200 ns at an address voltage of 35 V, while the related dynamic driving margin is wide under a low address voltage condition. The related phenomena are also examined using the Vt close-curve method.

We designed a CMOS image sensor capable of capturing variably smoothed images. This sensor uses a negative-feedback technique to set photodiode (PD) capacitance in the pixel circuit to any intermediate voltage during charge accumulation and it provides a neighboring-pixel operation by using their average value when resetting the PD capacitance. Smoothing-filter coefficients are changed by adjusting timing of the pixel-readout and neighboring-pixels operations. The performance of the proposed sensor was evaluated by SPICE simulation and numerical analysis.

A new dual-slope ramp (DSR) reset waveform is proposed to improve the dark room contrast ratio in AC-PDPs. The proposed reset waveform has two different voltage slopes during a ramp-up period. The first voltage slope lower than the conventional ramp voltage slope plays a role in producing the priming particles under the low background luminance, which is considered to be a kind of pre-reset discharge. On the other hand, the second voltage slope higher than the conventional ramp voltage slope produces a stable reset discharge due to the presence of the priming particles, but gives rise to a slight increase in the background luminance. Thus, a bias voltage is also applied during a part of the second voltage-slope period to adjust the background luminance and address discharge characteristics. As a result, the proposed dual-slope reset waveform can lower the background luminance without causing the discharge instability, thereby improving the high dark room contrast ratio of an AC-PDP without reducing the address voltage margin.

This paper proposes a novel auto-reset forward DC-DC converter with inductor-switching technique to obtain the high performance by means of zero voltage switching and the fast transient response at steep load variations. The performance of the forward converter is strongly depending on the transformer reset-method. The Auto-reset method is used to recover the energy stored in leakage inductances of the transformer to the power supply and makes sure the zero voltage switching. Furthermore fast transient response is achieved by applying the inductor-switching technique, which keeps the output voltage constant in case of heavy burden load changes. The design of the proposed concept is verified by experiment of 12 V input and 1.8 V/12 A output.

A Power on Reset signal generation circuit referencing threshold voltage without standby current consumption has been proposed. The POR signal is generated when supply voltage is larger than the sum of threshold voltages of N- and P-MOSFET.

In this era of System-On-a-Chip (SOC) technology, a designable initial state is required. Thus, embedding low voltage and low power Power-On-Reset (POR) circuit on the SOC chip is important for the portable device. This paper proposes a new POR circuit with process and temperature compensations. A band-gap reference is used in this circuit to reduce the effect of the temperature and process variations. With 200 mV hysteretic design provides robust noise immunity against voltage fluctuations on the power supply. The POR circuit has been designed, simulated, and implemented. A test chip has been fabricated by using 0.18 µm single-poly triple-metal CMOS logical process. Measurement results show the rise threshold voltage Vrr has only a 3% variation under the temperature range from -40 to 125. The power consumption is 39 mW at the 1.8 V power supply. The chip size of the POR is 62 mm280 mm. Thus, this POR circuit has a great potential to apply to a low power supply system.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

A timer-based scheme is proposed to manage information within terminal and service profiles for both incall registration/deregistration of UPT users and incall registration resets of terminal owners. In the timer-based scheme, information related to incall registration for a UPT user in a terminal profile is deleted due to a timer expiration without accessing the terminal profile. The performance of the timer-based scheme is compared with the previously proposed request-based scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal. Even though provision of the timer-based scheme requires the modification of incoming call delivery procedure, the timer-based scheme can reduce both the total cost and the number of terminal profile accesses compared to the previously proposed request-based scheme.

In universal personal telecommunication (UPT) environments, UPT networks retain information related to incall/outcall registration in UPT user service profiles in order to provide incoming UPT calls for UPT users in any location who have registered at a terminal. As UPT networks support incall registration, terminal users can be different from terminal owners, and several UPT users can register for incoming calls on a single terminal. Therefore, appropriate third-party protection procedures are needed to protect the rights of terminal owners. A terminal profile database can be used to store information regarding terminal states and incall UPT users registered on a terminal in order to enable third-party protection procedures. In order to manage information within both the terminal profile and the service profile, we propose a request-based scheme for incall registration/deregistration of UPT users and incall registration resets of terminal owners. We evaluate the performance of the scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

In this paper, we study the knowledge tightness of zero-knowledge proofs. To this end, we present a new measure for the knowledge tightness of zero-knowledge proofs and show that if a language L has a bounded round zero-knowledge proof with knowledge tightness t(|x|) 2 - |x|-c for some c 0, then L BPP and that any language L AM has a bounded round zero-knowledge proof with knowledge tightness t(|x|) 2-2-O(|x|) under the assumption that collision intractable hash functions exist. This implies that in the case of a bounded round zero-knowledge proof for a language L BPP, the optimal knowledge tightness is "2" unless AM = BPP. In addition, we show that any language L IP has an unbounded round zero-knowledge proof with knowledge tightness t(|x|) 1.5 under the assumption that nonuniformly secure probabilistic encryptions exist.