IEICE TRANSACTIONS on Electronics
A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
Summary :
A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.1 pp.102-109
- Publication Date
- 2011/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.102
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Keyword
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Shunichi KAERIYAMA, Mikihiro KAJITA, Masayuki MIZUNO, "A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 1, pp. 102-109, January 2011, doi: 10.1587/transele.E94.C.102.
Abstract: A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.102/_p
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@ARTICLE{e94-c_1_102,
author={Shunichi KAERIYAMA, Mikihiro KAJITA, Masayuki MIZUNO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests},
year={2011},
volume={E94-C},
number={1},
pages={102-109},
abstract={A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.},
keywords={},
doi={10.1587/transele.E94.C.102},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
T2 - IEICE TRANSACTIONS on Electronics
SP - 102
EP - 109
AU - Shunichi KAERIYAMA
AU - Mikihiro KAJITA
AU - Masayuki MIZUNO
PY - 2011
DO - 10.1587/transele.E94.C.102
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2011
AB - A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.
ER -
English
