IEICE TRANSACTIONS on Electronics
A Fractional-N PLL with Dual-Mode Detector and Counter
Summary :
A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.12 pp.1887-1890
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1887
- Type of Manuscript
- BRIEF PAPER
- Category
- Integrated Electronics
Authors
Keyword
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Fitzgerald Sungkyung PARK, Nikolaus KLEMMER, "A Fractional-N PLL with Dual-Mode Detector and Counter" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 12, pp. 1887-1890, December 2012, doi: 10.1587/transele.E95.C.1887.
Abstract: A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1887/_p
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@ARTICLE{e95-c_12_1887,
author={Fitzgerald Sungkyung PARK, Nikolaus KLEMMER, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fractional-N PLL with Dual-Mode Detector and Counter},
year={2012},
volume={E95-C},
number={12},
pages={1887-1890},
abstract={A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.},
keywords={},
doi={10.1587/transele.E95.C.1887},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - A Fractional-N PLL with Dual-Mode Detector and Counter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1887
EP - 1890
AU - Fitzgerald Sungkyung PARK
AU - Nikolaus KLEMMER
PY - 2012
DO - 10.1587/transele.E95.C.1887
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2012
AB - A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.
ER -
English
