Self-dithered digital delta-sigma modulators (DDSMs) are commonly used in fractional-N frequency synthesizers due to their ability to eliminate unwanted spurs from the synthesizer’s spectra without requiring additional hardware. However, when operating with a low-bit input, self-dithered DDSMs can still suffer from spurious tones at certain inputs. In this paper, we propose a self-dithered MASH 1-1-1-1 structure to mitigate the spur issue in the self-dithered MASH DDSMs. The proposed self-dithered MASH 1-1-1-1 suppresses the spurs with shaped dithering and achieves 4th order noise shaping.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rd- and 2nd-order.