IEICE TRANSACTIONS on Electronics
Layout-Aware Variability Characterization of CMOS Current Sources
Summary :
Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.696-705
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.696
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
- Category
Authors
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Bo LIU, Bo YANG, Shigetoshi NAKATAKE, "Layout-Aware Variability Characterization of CMOS Current Sources" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 696-705, April 2012, doi: 10.1587/transele.E95.C.696.
Abstract: Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.696/_p
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@ARTICLE{e95-c_4_696,
author={Bo LIU, Bo YANG, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Layout-Aware Variability Characterization of CMOS Current Sources},
year={2012},
volume={E95-C},
number={4},
pages={696-705},
abstract={Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.},
keywords={},
doi={10.1587/transele.E95.C.696},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Layout-Aware Variability Characterization of CMOS Current Sources
T2 - IEICE TRANSACTIONS on Electronics
SP - 696
EP - 705
AU - Bo LIU
AU - Bo YANG
AU - Shigetoshi NAKATAKE
PY - 2012
DO - 10.1587/transele.E95.C.696
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.
ER -
English
