A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter

Guo-Ming SUNG; Ying-Tzu LAI; Yueh-Hung HOU

doi:10.1587/transele.E96.C.595

A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter

Guo-Ming SUNG, Ying-Tzu LAI, Yueh-Hung HOU

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This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e₂). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm², respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.595-603

Publication Date: 2013/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.595

Type of Manuscript: PAPER

Category: Electronic Circuits

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Guo-Ming SUNG, Ying-Tzu LAI, Yueh-Hung HOU, "A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 4, pp. 595-603, April 2013, doi: 10.1587/transele.E96.C.595.
Abstract: This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e₂). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm², respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.595/_p

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@ARTICLE{e96-c_4_595,
author={Guo-Ming SUNG, Ying-Tzu LAI, Yueh-Hung HOU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter},
year={2013},
volume={E96-C},
number={4},
pages={595-603},
abstract={This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e₂). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm², respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.},
keywords={},
doi={10.1587/transele.E96.C.595},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter
T2 - IEICE TRANSACTIONS on Electronics
SP - 595
EP - 603
AU - Guo-Ming SUNG
AU - Ying-Tzu LAI
AU - Yueh-Hung HOU
PY - 2013
DO - 10.1587/transele.E96.C.595
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e₂). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm², respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.
ER -