This work develops a third-order multibit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18µm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

A finite impulse response (FIR) core based on the cascoded class AB SI technique is presented for low power wireless transceivers. Accomplished through both architectural and circuit developments, the filter's features include high speed, low power consumption, small silicon area and compatibility with standard CMOS process. For feasibility and performance assessments, an 8-tap 16 MS/s SI FIR filter with 5-bit coefficients and a 31-tap 80 MS/s SI matched filter (MF) for despreading task in future WCDMA receivers are demonstrated via simulations.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

We have proposed a current-cut switched-current matched filter (CC-SIMF) for direct-sequence code-division multiple-access (DS-CDMA). The 256-chip CC-SIMF can achieve low power consumption of less than 10 mW under high-speed operation of more than 16 Mcps. To reduce the current transfer error accumulation, we propose a parallel SIMF configuration. A 128-chip SIMF using 0.8-µm Complementally Metal Oxide Semiconductor (CMOS) process has been designed and fabricated. Optimization of the current memory cell structure has been described. The correlation operation at 16 Mcps has been obtained using a 128-chip orthogonal m-sequence. The code phase separation performance for path diversity has been clearly observed. The power consumption has been significantly reduced using the current-cut method.

This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

In this paper, a novel chaos circuit with long working-life is proposed. The proposed circuit consists of NMOS-coupled discrete-time chaotic cell circuits. By employing chaos synchronization phenomenon, the proposed circuit can achieve long working-life. Since the proposed circuit is less susceptible to breakdown, the rate of the acceptable product for chaos IC can be improved. Furthermore, thanks to the coupling by using NMOSFET's, the loss of the connection line between chaotic cell circuits can be controlled electronically. Therefore, the proposed system designed by using switched-current (SI) techniques is useful as an experimental tool to analyze chaos synchronization phenomena. The validity of the proposed circuits is confirmed by computer simulations and experiments.

In this letter, a simple design of a discrete-time chaos circuit realizing a tent map is proposed. The proposed circuit can be constructed with 13 MOSFET's and 2 capacitors. Concerning the proposed circuit synthesized using switched-current (SI) techniques, the validity of the circuit design is analyzed by SPICE simulations. Furthermore, the proposed circuit is built with commercially-available IC's. The proposed circuit is integrable by a standard CMOS technology.

This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 µ m CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

A fully-differential switched-current (SI) circuit provided with clock-feedthrough (CFT) and common mode rejection and offset compensation schemes is described. Different from a conventional SI memory cell, it takes the difference between two differential inputs to deliver the balanced differential currents. Transistor level simulations and error analyses are given to demonstrate its performance.

In this paper, a new switched-current auto-tuning filter is proposed. Switched-current (SI) is a current-mode analog sampled-data circuit technique. An SI circuit can be realized using only standard digital CMOS technologies, and is capable of realizing high frequency circuits. The proposed filter is composed of SI-OTA (operational transconductance amplifier) integrators. The gain of an SI-OTA integrator can be electronically controlled by the bias current. The proposed filter is a current controlled filter (CCF) and a PLL technique was used as its tuning method. A 2nd-order SI auto-tuning low-pass filter with 100kHz cutoff frequency was designed assuming a 2µm CMOS process. The characteristics of this SI filter and its tuning characteristics were confirmed by SPICE simulations.