This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

We investigated single flux quantum sinc filters with multistage decimation structure in order to realize high-speed sinc filter operation. Second- and third-order (k=2, 3) sinc filters with a decimation factor N=2 were designed and confirmed their proper operations. These sinc filters with N=2 are utilized as elementary circuit blocks of our multistage decimation sinc filters with N=2M, where M indicates the number of the stage of the decimation. As an example of the multistage decimation filter, we designed a k=2, N=4 sinc filter which was formed from a two-stage decimation structure using k=2, N=2 sinc filters, and confirmed its proper operation. The k=2, N=4 sinc filter consisted of 1372 Josephson junctions with the power consumption of 191 µW.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.