IEICE TRANSACTIONS on Electronics
Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers
Summary :
This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.838-849
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.838
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Hyunui LEE
Tokyo Institute of Technology
Masaya MIYAHARA
Tokyo Institute of Technology
Akira MATSUZAWA
Tokyo Institute of Technology
Keyword
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Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA, "Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 838-849, June 2013, doi: 10.1587/transele.E96.C.838.
Abstract: This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.838/_p
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@ARTICLE{e96-c_6_838,
author={Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers},
year={2013},
volume={E96-C},
number={6},
pages={838-849},
abstract={This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.},
keywords={},
doi={10.1587/transele.E96.C.838},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 838
EP - 849
AU - Hyunui LEE
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2013
DO - 10.1587/transele.E96.C.838
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.
ER -
English
