A 0.9 V 1.5 mW Continuous-Time ΔΣ Modulator for W-CDMA
Summary :
This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.2 pp.461-468
- Publication Date
- 2005/02/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.2.461
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Takeshi UENO, Tetsuro ITAKURA, "A 0.9 V 1.5 mW Continuous-Time ΔΣ Modulator for W-CDMA" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 2, pp. 461-468, February 2005, doi: 10.1093/ietfec/e88-a.2.461.
Abstract: This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.2.461/_p
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@ARTICLE{e88-a_2_461,
author={Takeshi UENO, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 0.9 V 1.5 mW Continuous-Time ΔΣ Modulator for W-CDMA},
year={2005},
volume={E88-A},
number={2},
pages={461-468},
abstract={This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.},
keywords={},
doi={10.1093/ietfec/e88-a.2.461},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A 0.9 V 1.5 mW Continuous-Time ΔΣ Modulator for W-CDMA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 461
EP - 468
AU - Takeshi UENO
AU - Tetsuro ITAKURA
PY - 2005
DO - 10.1093/ietfec/e88-a.2.461
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2005
AB - This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.
ER -
English
