High-Speed Low Input Impedance CMOS Current Comparator

Varakorn KASEMSUWAN; Surachet KHUCHAROENSIN

doi:10.1093/ietfec/e88-a.6.1549

High-Speed Low Input Impedance CMOS Current Comparator

Varakorn KASEMSUWAN, Surachet KHUCHAROENSIN

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A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.6 pp.1549-1553

Publication Date: 2005/06/01

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DOI: 10.1093/ietfec/e88-a.6.1549

Type of Manuscript: PAPER

Category: Analog Signal Processing

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Varakorn KASEMSUWAN, Surachet KHUCHAROENSIN, "High-Speed Low Input Impedance CMOS Current Comparator" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 6, pp. 1549-1553, June 2005, doi: 10.1093/ietfec/e88-a.6.1549.
Abstract: A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.6.1549/_p

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@ARTICLE{e88-a_6_1549,
author={Varakorn KASEMSUWAN, Surachet KHUCHAROENSIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed Low Input Impedance CMOS Current Comparator},
year={2005},
volume={E88-A},
number={6},
pages={1549-1553},
abstract={A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.},
keywords={},
doi={10.1093/ietfec/e88-a.6.1549},
ISSN={},
month={June},}

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TY - JOUR
TI - High-Speed Low Input Impedance CMOS Current Comparator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1549
EP - 1553
AU - Varakorn KASEMSUWAN
AU - Surachet KHUCHAROENSIN
PY - 2005
DO - 10.1093/ietfec/e88-a.6.1549
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2005
AB - A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.
ER -