Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule

Kazunori SHIMIZU; Tatsuyuki ISHIKAWA; Nozomu TOGAWA; Takeshi IKENAGA; Satoshi GOTO

doi:10.1093/ietfec/e89-a.4.969

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule

Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO

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In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.969-978

Publication Date: 2006/04/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.4.969

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)

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Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO, "Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 4, pp. 969-978, April 2006, doi: 10.1093/ietfec/e89-a.4.969.
Abstract: In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.969/_p

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@ARTICLE{e89-a_4_969,
author={Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule},
year={2006},
volume={E89-A},
number={4},
pages={969-978},
abstract={In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.},
keywords={},
doi={10.1093/ietfec/e89-a.4.969},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 969
EP - 978
AU - Kazunori SHIMIZU
AU - Tatsuyuki ISHIKAWA
AU - Nozomu TOGAWA
AU - Takeshi IKENAGA
AU - Satoshi GOTO
PY - 2006
DO - 10.1093/ietfec/e89-a.4.969
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.
ER -