IEICE TRANSACTIONS on Fundamentals
A Relocation Method for Circuit Modifications
Summary :
In this paper, we propose a novel migration method. In this method, the resultant placement retains the structure of the original placement, called model placement, as much as possible. For this purpose, we minimize the sum of the difference in area between the model placement and the relocated one and the total amount of displacement between them. Moreover, to achieve a short runtime, we limit the solution space and change the packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less runtime than that realized by naive simulated annealing.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2743-2751
- Publication Date
- 2007/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.12.2743
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Synthesis
Authors
Keyword
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Kunihiko YANAGIBASHI, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, "A Relocation Method for Circuit Modifications" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 12, pp. 2743-2751, December 2007, doi: 10.1093/ietfec/e90-a.12.2743.
Abstract: In this paper, we propose a novel migration method. In this method, the resultant placement retains the structure of the original placement, called model placement, as much as possible. For this purpose, we minimize the sum of the difference in area between the model placement and the relocated one and the total amount of displacement between them. Moreover, to achieve a short runtime, we limit the solution space and change the packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less runtime than that realized by naive simulated annealing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2743/_p
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@ARTICLE{e90-a_12_2743,
author={Kunihiko YANAGIBASHI, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Relocation Method for Circuit Modifications},
year={2007},
volume={E90-A},
number={12},
pages={2743-2751},
abstract={In this paper, we propose a novel migration method. In this method, the resultant placement retains the structure of the original placement, called model placement, as much as possible. For this purpose, we minimize the sum of the difference in area between the model placement and the relocated one and the total amount of displacement between them. Moreover, to achieve a short runtime, we limit the solution space and change the packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less runtime than that realized by naive simulated annealing.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2743},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Relocation Method for Circuit Modifications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2743
EP - 2751
AU - Kunihiko YANAGIBASHI
AU - Yasuhiro TAKASHIMA
AU - Yuichi NAKAMURA
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2743
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - In this paper, we propose a novel migration method. In this method, the resultant placement retains the structure of the original placement, called model placement, as much as possible. For this purpose, we minimize the sum of the difference in area between the model placement and the relocated one and the total amount of displacement between them. Moreover, to achieve a short runtime, we limit the solution space and change the packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less runtime than that realized by naive simulated annealing.
ER -
English
