IEICE TRANSACTIONS on Fundamentals
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
Summary :
Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.5 pp.1028-1037
- Publication Date
- 2007/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.5.1028
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
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Yibo WANG, Yici CAI, Xianlong HONG, Yi ZOU, "Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 5, pp. 1028-1037, May 2007, doi: 10.1093/ietfec/e90-a.5.1028.
Abstract: Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.5.1028/_p
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@ARTICLE{e90-a_5_1028,
author={Yibo WANG, Yici CAI, Xianlong HONG, Yi ZOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration},
year={2007},
volume={E90-A},
number={5},
pages={1028-1037},
abstract={Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.},
keywords={},
doi={10.1093/ietfec/e90-a.5.1028},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1028
EP - 1037
AU - Yibo WANG
AU - Yici CAI
AU - Xianlong HONG
AU - Yi ZOU
PY - 2007
DO - 10.1093/ietfec/e90-a.5.1028
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2007
AB - Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.
ER -
English
