Timing Criticality for Timing Yield Optimization

Hyoun Soo PARK; Wook KIM; Dai Joon HYUN; Young Hwan KIM

doi:10.1093/ietfec/e91-a.12.3497

Timing Criticality for Timing Yield Optimization

Hyoun Soo PARK, Wook KIM, Dai Joon HYUN, Young Hwan KIM

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Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3497-3505

Publication Date: 2008/12/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.12.3497

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Device and Circuit Modeling and Analysis

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Hyoun Soo PARK, Wook KIM, Dai Joon HYUN, Young Hwan KIM, "Timing Criticality for Timing Yield Optimization" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 12, pp. 3497-3505, December 2008, doi: 10.1093/ietfec/e91-a.12.3497.
Abstract: Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3497/_p

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@ARTICLE{e91-a_12_3497,
author={Hyoun Soo PARK, Wook KIM, Dai Joon HYUN, Young Hwan KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing Criticality for Timing Yield Optimization},
year={2008},
volume={E91-A},
number={12},
pages={3497-3505},
abstract={Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3497},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Timing Criticality for Timing Yield Optimization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3497
EP - 3505
AU - Hyoun Soo PARK
AU - Wook KIM
AU - Dai Joon HYUN
AU - Young Hwan KIM
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3497
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.
ER -