This paper is to propose a digital watermarking to protect the ownership of a video content which is compressed by H.264/AVC main profile. This scheme intends to be performed during the CABAC (Context-based Adaptive Binary Arithmetic Coding) process which is the entropy coding of the main profile. It uses the contexts extracted during the context modeling process of CABAC to position the watermark bits by simply checking the context values and determining the coefficients. The watermarking process is also as simple as replacing the watermark bit with the LSB (Least Significant Bit) of the corresponding coefficient to be watermarked. Experimental results from applying this scheme and attacking in various ways such as blurring, sharpening, cropping, Gaussian noise addition, and geometrical modification showed that the watermark embedded by this scheme has very high imperceptibility and robustness to the attacks. Thus, we expect it to be used as a good watermarking scheme, especially in the area that the watermarking should be performed during the compression process with requiring minimal amount of process for watermarking.

In this paper, a new bandwidth allocation scheme is proposed based on the Mechanism Design (MD); MD is a branch of game theory that stimulates rational users to behave cooperatively for a global goal. The proposed scheme consists of bandwidth adaptation, call admission control and pricing computation algorithms to improve network performance. These algorithms are designed based on the adaptive online approach and work together to maximize bandwidth efficiency economically. A simulation shows that the proposed scheme can satisfy contradictory requirements and so provide well-balanced network performance.

Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.

A burst of social network services increases the need for in-depth analysis of network activities. Privacy breach for network participants is a concern in such analysis efforts. This paper investigates structural and property changes via several privacy preserving methods (anonymization) for social network. The anonymized social network does not follow the power-law for node degree distribution as the original network does. The peak-hop for node connectivity increases at most 1 and the clustering coefficient of neighbor nodes shows 6.5 times increases after anonymization. Thus, we observe inconsistency of privacy preserving methods in social network analysis.

In this paper we propose a subsequence matching algorithm that supports moving average transform of arbitrary order in time-series databases. Moving average transform reduces the effect of noise and has been used in many areas such as econometrics since it is useful in finding the overall trends. The proposed algorithm extends the existing subsequence matching algorithm proposed by Faloutsos et al. (SUB94 in short). If we applied the algorithm without any extension, we would have to generate an index for each moving average order and would have serious storage and CPU time overhead. In this paper we tackle the problem using the notion of index interpolation. Index interpolation is defined as a searching method that uses one or more indexes generated for a few selected cases and performs searching for all the cases satisfying some criteria. The proposed algorithm, which is based on index interpolation, can use only one index for a pre-selected moving average order k and performs subsequence matching for arbitrary order m ( k). We prove that the proposed algorithm causes no false dismissal. The proposed algorithm can also use more than one index to improve search performance. The algorithm works better with smaller selectivities. For selectivities less than 10-2, the degradation of search performance compared with the fully-indexed case--which is equivalent to SUB94--is no more than 33.0% when one index is used, and 17.2% when two indexes are used. Since the queries with smaller selectivities are much more frequent in general database applications, the proposed algorithm is suitable for practical situations.

A new design and experimental results of a microstrip-fed ultra-wideband Fermi antenna at millimeter-wave frequencies are presented. By utilizing a new microstrip-to-CPS balun (or transition), which provides wider bandwidth than conventional planar balun, the design of microstrip-fed Fermi antenna is greatly simplified. The proposed Fermi antenna demonstrates ultra-wideband performance for the frequency range of 23 to over 58 GHz with the antenna gain of 12 to 14 dBi and low sidelobe levels. This design yields highly effective solutions to various millimeter-wave phased-arrays and imaging systems.

A direct-mapped cache takes less time for accessing data than a set-associative cache because the time needed for selecting a cache line among the set is not necessary. The hit ratio of a direct-mapped cache, however, is lower due to the conflict misses caused by mapping multiple addresses to the same cache line. Addressing cache memory by virtual addresses reduces the cache access time by eliminating the time needed for address translation. The synonym problem in virtual cache necessitates an additional field in the cache tag to denote the process to which cache line belongs. In this paper, we propose a new virtual cache architecture whose average access time is almost the same as the direct-mapped caches while the hit ratio is the same as the set-associative cashes. A victim for cache replacement is selected from those that belong to a process which is most remote from being scheduled. The entire cache memory is divided into n banks, and each process is assigned to a bank. Then, each process runs on the assigned bank, and the cache behaves like a direct-mapped cache. Trace-driven simulations confirm that the new scheme removes almost as many conflict misses as does the set-associative cache, while cache access time is similar to a direct-mapped cache.

This paper presents new encoding methods for the binary genetic algorithm (BGA) and new converting methods for the real-coded genetic algorithm (RCGA). These methods are developed for the specific case in which some parameters have to be searched in wide ranges since their actual values are not known. The oversampling effect which occurs at large values in the wide range search are reduced by adjustment of resolutions in mantissa and exponent of real numbers mapped by BGA. Owing to an intrinsic similarity in chromosomal operations, the proposed encoding methods are also applied to RCGA with remapping (converting as named above) from real numbers generated in RCGA. A simple probabilistic analysis and benchmark with two ill-scaled test functions are carried out. System identification of a simple electrical circuit is also undertaken to testify effectiveness of the proposed methods to real world problems. All the optimization results show that the proposed encoding/converting methods are more suitable for problems with ill-scaled parameters or wide parameter ranges for searching.

In this paper, a new power control scheme is proposed to maximize the network throughput with fairness provisioning. Based on the Stackelberg game model, the proposed scheme consists of two control mechanisms; user-level and system-level mechanisms. Control decisions in each mechanism act cooperatively and collaborate with each other to satisfy efficiency and fairness requirements. Simulation results demonstrate that the proposed scheme has excellent network performance, while other schemes cannot offer such an attractive performance balance.

This paper proposes a new computational optimization method modified from the dynamic encoding algorithm for searches (DEAS). Despite the successful optimization performance of DEAS for both benchmark functions and parameter identification, the problem of exponential computation time becomes serious as problem dimension increases. The proposed optimization method named univariate DEAS (uDEAS) is especially implemented to reduce the computation time using a univariate local search scheme. To verify the algorithmic feasibility for global optimization, several test functions are optimized as benchmark. Despite the simpler structure and shorter code length, function optimization performance show that uDEAS is capable of fast and reliable global search for even high dimensional problems.

This paper proposed a watermarking algorithm for image, which assumed an image compression based on DWT (Discrete Wavelet Transform). To reduce the amount of computation, this algorithm selects the watermarking positions by a threshold table which is statistically established from computing the energy correlation of the corresponding wavelet coefficients. The proposed algorithm can operate in a real-time if the image compression process operates in a real-time because the watermarking process was designed to operate in parallel with the compression process. Also it improves the property of losing the watermak and reducing the compresson ratio by the quantization and Huffman coding steps. It was done by considering the sign of the coefficients and the change in the value for watermarking. Visually recognizable pattern such as a binary image were used as the watermark. The experimental results showed that the proposed algorithm satisfied the properties of robustness and imperceptibility that are the major conditions of watermarking.

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.

New multimedia services over cellular/WLAN overlay networks require different Quality of Service (QoS) levels. Therefore, an efficient network management system is necessary in order to realize QoS sensitive multimedia services while enhancing network performance. In this paper, we propose a new online network management framework for overlay networks. Our online approach to network management exhibits dynamic adaptability, flexibility, and responsiveness to the traffic conditions in multimedia networks. Simulation results indicate that our proposed framework can strike the appropriate balance between performance criteria under widely varying diverse traffic loads.

The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].

This paper proposed a new watermarking algorithm and implementation in hardware, by which the watermarking process and an image compression process can operate in conjunction, in parallel, and/or without degrading the performance of the compression process. The goal of the proposed watermarking scheme is to provide the bases to insist the ownership and to authenticate integrity of the watermark-embedded image by detecting the errors and their positions without the original image (blind watermarking). Our watermarking scheme is to replace the watermark with one or several bit-plane(s) of the DC subband after 2DDWT (2-Dimensional Discrete Wavelet Transform) decomposition which is the basic transformation in DWT-based image compression such as JPEG2000. If more than one bit-plane is involved, the position to embed each watermark bit is randomly selected among the bit-planes by a random number generated with an LFSR (Linear Feedback Shift Register). Experimental results showed that for all the considered attacks except the high compression by JPEG, the error ratios in the extracted watermarks by our algorithm were below 3% and the extracted watermarks were unambiguously recognizable in all the cases. The hardware (FPGA)-implemented result could operate stably in 82 MHz clock frequency. This hardware was merged to DWT-based image compression codec which runs in a real-time in 66 MHz of clock frequency. This resulted in the real-time operation for codec and watermarking together in 66 MHz of clock frequency. The watermarking scheme used 4,037 LABs (24%) of the hardware resource of APEX20KC EP20K400CF672-7 from Altera.

Recently, cooperative spectrum sensing is being studied to greatly improve the sensing performance of cognitive radio networks. To develop an adaptable cooperative sensing algorithm, an important issue is how to properly induce selfish users to participate in spectrum sensing work. In this paper, a new cognitive radio spectrum sharing scheme is developed by employing the trust-based bargaining model. The proposed scheme dynamically adjusts bargaining powers and adaptively shares the available spectrum in real-time online manner. Under widely different and diversified network situations, this approach is so dynamic and flexible that it can adaptively respond to current network conditions. Simulation results demonstrate that the proposed scheme can obtain better network performance and bandwidth efficiency than existing schemes.

This letter describes the development and implementation of the lane detection system accelerated by the neuromorphic hardware. Because the neuromorphic hardware has inherently parallel nature and has constant output latency regardless the size of the knowledge, the proposed lane detection system can recognize various types of lanes quickly and efficiently. Experimental results using the road images obtained in the actual driving environments showed that white and yellow lanes could be detected with an accuracy of more than 94 percent.

In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYSTM and SPWTM.

In this paper, we proposed an efficient coding method for digital hologram (fringe pattern) acquired with a CCD camera or by computer generation using multi-view prediction and MPEG video compression standard techniques. It processes each R, G, or B color component separately. The basic processing unit is a partial image segmented as the size of MN. Each partial image retains the information of the whole object. This method generates an assembled image for a column of the segmented and frequency-transformed partial images, which is the basis of the coding process. That is, a motion estimation and compensation technique of MPEG is applied between the reconstructed images from the assembled images with the disparities found during generation of assembled image and the original partial images. Therefore the compressed results are the disparity of each partial image to form the assembled image for the corresponding column, assembled image, and the motion vectors and the compensated image for each partial image. The experimental results with the implemented algorithm showed that the proposed method has NC (Normalized Correlation) values about 4% higher than the previous method at the same compression ratios, which convinced us that ours has better compression efficiency. Consequently, the proposed method is expected to be used effectively in the application areas to transmit or store in digital format the digital hologram data.