VLSI Implementation of a Complete Pipeline MMSE Detector for a 4<cd0215f.gif>4 MIMO-OFDM Receiver

Shingo YOSHIZAWA; Yasushi YAMAUCHI; Yoshikazu MIYANAGA

doi:10.1093/ietfec/e91-a.7.1757

VLSI Implementation of a Complete Pipeline MMSE Detector for a 44 MIMO-OFDM Receiver

Shingo YOSHIZAWA, Yasushi YAMAUCHI, Yoshikazu MIYANAGA

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This paper presents a VLSI architecture of MMSE detection in a 44 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.7 pp.1757-1762

Publication Date: 2008/07/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.7.1757

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Shingo YOSHIZAWA, Yasushi YAMAUCHI, Yoshikazu MIYANAGA, "VLSI Implementation of a Complete Pipeline MMSE Detector for a 44 MIMO-OFDM Receiver" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 7, pp. 1757-1762, July 2008, doi: 10.1093/ietfec/e91-a.7.1757.
Abstract: This paper presents a VLSI architecture of MMSE detection in a 44 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.7.1757/_p

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@ARTICLE{e91-a_7_1757,
author={Shingo YOSHIZAWA, Yasushi YAMAUCHI, Yoshikazu MIYANAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Implementation of a Complete Pipeline MMSE Detector for a 44 MIMO-OFDM Receiver},
year={2008},
volume={E91-A},
number={7},
pages={1757-1762},
abstract={This paper presents a VLSI architecture of MMSE detection in a 44 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.},
keywords={},
doi={10.1093/ietfec/e91-a.7.1757},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - VLSI Implementation of a Complete Pipeline MMSE Detector for a 44 MIMO-OFDM Receiver
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1757
EP - 1762
AU - Shingo YOSHIZAWA
AU - Yasushi YAMAUCHI
AU - Yoshikazu MIYANAGA
PY - 2008
DO - 10.1093/ietfec/e91-a.7.1757
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2008
AB - This paper presents a VLSI architecture of MMSE detection in a 44 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.
ER -