Timing Verification of Logic Circuits with Combined Delay Model

Shinji KIMURA; Shigemi KASHIMA; Hiromasa HANEDA

Timing Verification of Logic Circuits with Combined Delay Model

Shinji KIMURA, Shigemi KASHIMA, Hiromasa HANEDA

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The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (d_m), the maximum delay time (d_M), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between d_m and d_M. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.10 pp.1230-1238

Publication Date: 1992/10/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Shinji KIMURA, Shigemi KASHIMA, Hiromasa HANEDA, "Timing Verification of Logic Circuits with Combined Delay Model" in IEICE TRANSACTIONS on Fundamentals, vol. E75-A, no. 10, pp. 1230-1238, October 1992, doi: .
Abstract: The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (d_m), the maximum delay time (d_M), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between d_m and d_M. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_10_1230/_p

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@ARTICLE{e75-a_10_1230,
author={Shinji KIMURA, Shigemi KASHIMA, Hiromasa HANEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing Verification of Logic Circuits with Combined Delay Model},
year={1992},
volume={E75-A},
number={10},
pages={1230-1238},
abstract={The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (d_m), the maximum delay time (d_M), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between d_m and d_M. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Timing Verification of Logic Circuits with Combined Delay Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1230
EP - 1238
AU - Shinji KIMURA
AU - Shigemi KASHIMA
AU - Hiromasa HANEDA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1992
AB - The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (d_m), the maximum delay time (d_M), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between d_m and d_M. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.
ER -