Linear Time Fault Simulation Algorithm Using a Content Addressable Memory

Nagisa ISHIURA; Shuzo YAJIMA

Linear Time Fault Simulation Algorithm Using a Content Addressable Memory

Nagisa ISHIURA, Shuzo YAJIMA

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This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n²) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.3 pp.314-320

Publication Date: 1992/03/25

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Type of Manuscript: Special Section INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)

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Nagisa ISHIURA, Shuzo YAJIMA, "Linear Time Fault Simulation Algorithm Using a Content Addressable Memory" in IEICE TRANSACTIONS on Fundamentals, vol. E75-A, no. 3, pp. 314-320, March 1992, doi: .
Abstract: This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n²) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_3_314/_p

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@ARTICLE{e75-a_3_314,
author={Nagisa ISHIURA, Shuzo YAJIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Linear Time Fault Simulation Algorithm Using a Content Addressable Memory},
year={1992},
volume={E75-A},
number={3},
pages={314-320},
abstract={This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n²) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 314
EP - 320
AU - Nagisa ISHIURA
AU - Shuzo YAJIMA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1992
AB - This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n²) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.
ER -