IEICE TRANSACTIONS on Fundamentals
Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Summary :
This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.6 pp.712-719
- Publication Date
- 1992/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
- Category
- Robot Electronics
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Bumchul KIM, Michitaka KAMEYAMA, Tatsuo HIGUCHI, "Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks" in IEICE TRANSACTIONS on Fundamentals,
vol. E75-A, no. 6, pp. 712-719, June 1992, doi: .
Abstract: This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_6_712/_p
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@ARTICLE{e75-a_6_712,
author={Bumchul KIM, Michitaka KAMEYAMA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks},
year={1992},
volume={E75-A},
number={6},
pages={712-719},
abstract={This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 712
EP - 719
AU - Bumchul KIM
AU - Michitaka KAMEYAMA
AU - Tatsuo HIGUCHI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1992
AB - This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.
ER -
English
