This paper treats the synthesis of immittance floatator using nullors. Eight sets of circuit equations for realizing immittance floatators and their nullor (nullator-norator) representations are given. By replacing nullors with active elements such as biporlar junction transistors (BJTs), current conveyors (CCIIs), operational amplifiers (OAs) and operational transconductance amplifiers (OTAs), the immittance floatators can be derived. The development is important because it enables one to convert the present wealth of knowledge concerning grounded immittance simulation networks into floating immittance simulation networks. Using immittance floatators, we can obtain not only the floating form of 1-port but also that of 2-port networks. Novel circuits use solely minus-type norators. Using one-type (minus- or plus-type) norators greatly simplifies the simulation circuit. In the case of an immittance floatator using CCIIs as the active elements, the effects of nonideal CCIIs and sensitivities are given. Many circuits can be systematically derived using nullor technique.

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

For a realization of a DC-DC converter using no magnetic devices, a new switched capacitor (SC) transformer is introduced, which gives voltage ratios by Fibonacci series corresponding to the stages. This transformer is connected in cascade by each basic block which is assembled by a capacitor and three MOSFET switches. This operates on a simple two-phase clock and has a large step-up or step-down voltage ratio in spite of its simple configuration. The characteristics of this transformer with n stages of basic block are derived and calculated by means of a 4 4 cascade matrix. The optimal arrangement of each stage's capacitances is shown to reduce the SC resistance by about 20%. The simulation results are compared with the characteristics of a prototype transformer with four stages (8 times step-up ratio). Its power efficiency achieves 88% in case of 97 V output voltage, 0.2 A output current, and 100 kHz switching frequency. Lastly, the proposed SC transformer is compared and discussed with other typical SC transformers.

This paper extends an earlier study on the T-Model neural network to its collective computational properties. We present arguments that it is necessary to use the half-interconnected T-Model networks rather than the fully-interconnected Hopfield model networks. The T-Model has been generated in response to a number of observed weaknesses in the Hopfield model. This paper identities these problems and show how the T-Model overcomes them. The T-Model network is essentially a feedforward network which does not produce a local minimum for computations. A concept for understanding the dynamics of the T-Model neural circuit is presented and its performance is also compared with the Hopfield model. The T-Model neural circuit is implemented and tested with standard CMOS technology. Simulations and experiments show that the T-Model allows immense collective network computations and does not produce a local minimum. High densities comparable to that of the Hopfield model implementations have also been achieved.

In this paper we study the problem of scheduling parallel program modules onto an MPS (message passing multiprocessor system) so as to minimize the total execution time. Each node in the interconnection network of the MPS has buffers at its input ports to store messages waiting for the transmission. An algorithm for finding a route which minimizes the communication delay of a message to be sent between a processor-pair is first given. Next, we present heuristic algorithms for scheduling program modules onto the MPS. These algorithms use the above routing algorithm. The performances of the proposed algorithms are estimated by using simulation experiments.

Location theory on networks is concerned with the problem of selecting the best location in a specified network for facilities. Many studies for the theory have been done. However, few studies treat location problems on networks from the standpoint of measuring the closeness between two vertices by the capacity (maximum flow value) between two vertices. This paper concerns location problems, called covering problems on flow networks. We define two types of covering problems on flow networks. We show that covering problems on undirected flow networks and a covering problem on directed flow networks are solved in polynomial times.

This paper describes the waveform relaxation (WR) algorithm with the under relaxation method based on the virtual state formulation (VSF) technique and the effect of multirate behavior in this algorithm. First, we present the virtual state relaxation method using VSF technique. Next, we introduce the VSF method into WR algorithm in order to exploit the multirate behavior. Furthermore, we construct the relaxation-based circuit simulator DESIRE2 and apply this simulator to the transient analysis of MOS circuits. Finally, we show that the present technique enables to use efficiently the multirate integration method in VSR and reduce the total simulation time without losing the waveform accuracy.

A fast scan-line algorithm for a raster-scan graphics display is proposed based on an observation that a sequence of successive image frames in animation mostly consists of still objects with relatively few moving objects. In the proposed algorithm, successive images are generated using the background image composed of still objects only, and moving image composed only of moving objects. The color of each pixel in the successive images is then determined by one, which is nearer from eye, between the two candidate pixels, where one is from the background image and the other is from the moving image. The background image is generated once in the whole process, while the moving image is generated for each time frame using an interpolation of two images generated at the start and end time of the given time interval. For the purpose of fast shadow generation, we classify the shadows into three groups, i.e., still shadows generated by still objects on still objects, moving shadows generated by moving objects on still objects, and composite shadows generated by both still objects and moving objects on moving objects. These shadows can be generated very quickly by utilizing the frame coherence. According to the experimental results, a speed up factor of 3.2 to 12.8, depending on the percentage of the moving objects among all objects, was obtained using our algorithm, compared to the conventional scheme not utilizing the frame-to-frame image coherence.

Fading is unavoidable in many communication systems such as urban and mobile radio systems. Fading, in principle, results in increased error in data communications. However, the random variation of received signal envelope due to natural fading divides the received signals into many different power level, a method known to improved utilization of ALOHA network due to capture effects. In this paper, we consider Nakagami fading model for the radio channel. We derive the exact form of capture probabilities and show that the probabilities can be modeled as semi-exponential model. Thus we can determine the channel capacity of ALOHA system with capture channel.

This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.

The F-matrix expressions of inverted-L-type four-terminal networks, each involving an element with the power-law conductivity σ(ω)ω^a (0a1) connected to a resistance R, an inductance L or a capacitance C, were derived using the standard procedures of Laplace transformation, indicating that the exponents of the complex angular frequency s, so far limited to the integers for the transmission circuits with finite elements, can be extended to the real numbers. The responses to a step voltage calculated show hysteretic behavior reflecting the resistance-capacitance ambivalent nature of the power-law conductivity.

A new Elastic-Block Matching Algorithm using bilinear space warping is proposed. In this scheme a convex quadrilateral, which minimizes a distortion measure against the current square block, is searched to compensate the shape deformation caused by a rigid body's 3 dimensional depth motion or rotation. The proposed algorithm gives a remarkable improvement in motion-compensated prediction compared with the conventional algorithm.

General estimation technique using covariance information is proposed for white Gaussian and white Gaussian plus coloured observation noises in linear stationary stochastic systems. Namely, autocovariance data of signal and coloured noise appear in a semi-degenerate kernel, which represents functional expression of the autocovariance data, in the current technique. Then the signal is estimated by directly using autocovariance data of signal and coloured noise. On the other hand, in the previous technique, the covariance information is expressed in the form of a semi-degenerate kernel, but its elements do not include any autocovariance data.

In this paper, we propose a multi-purpose proof system which enables a user remembering only one piece of secret data to perform various proof protocols. These proofs include identity proof, membership proof without disclosing identity, and combined identity and membership proof. When a user participates in a group, he will obtain a secret witness from the group administrator. Many secret witnesses can be combined into one piece of secret data. But the size of the secret data is independent of the number of the groups in which the user participates. Our system satisfies other desirable properties which were not attained by the previously proposed systems.

In this letter, introducing a highly accurate model for a real current mode DC-DC converter, an innovative design strategy is proposed in order to optimize circuit behavior in cases in which chaotic effects are present.