Estimation of short-Circuit Power Dissipation for Static CMOS Gates
Summary :
We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.3 pp.304-311
- Publication Date
- 1996/03/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
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Akio HIRATA, Hidetoshi ONODERA, Keikichi TAMARU, "Estimation of short-Circuit Power Dissipation for Static CMOS Gates" in IEICE TRANSACTIONS on Fundamentals,
vol. E79-A, no. 3, pp. 304-311, March 1996, doi: .
Abstract: We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_3_304/_p
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@ARTICLE{e79-a_3_304,
author={Akio HIRATA, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Estimation of short-Circuit Power Dissipation for Static CMOS Gates},
year={1996},
volume={E79-A},
number={3},
pages={304-311},
abstract={We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Estimation of short-Circuit Power Dissipation for Static CMOS Gates
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 304
EP - 311
AU - Akio HIRATA
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1996
AB - We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.
ER -
English
