IEICE TRANSACTIONS on Fundamentals
A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage
Summary :
Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.2 pp.261-266
- Publication Date
- 2000/02/25
- Publicized
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- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
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Khayrollah HADIDI, Masahiro SASAKI, Tadatoshi WATANABE, Daigo MURAMATSU, Takashi MATSUMOTO, "A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 261-266, February 2000, doi: .
Abstract: Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_261/_p
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@ARTICLE{e83-a_2_261,
author={Khayrollah HADIDI, Masahiro SASAKI, Tadatoshi WATANABE, Daigo MURAMATSU, Takashi MATSUMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage},
year={2000},
volume={E83-A},
number={2},
pages={261-266},
abstract={Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 261
EP - 266
AU - Khayrollah HADIDI
AU - Masahiro SASAKI
AU - Tadatoshi WATANABE
AU - Daigo MURAMATSU
AU - Takashi MATSUMOTO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
ER -
English
