A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.

This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.

Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.