A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
Summary :
This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.2 pp.267-271
- Publication Date
- 2000/02/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
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Hyuk-Jun SUNG, Kwang Sub YOON, "A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 267-271, February 2000, doi: .
Abstract: This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_267/_p
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@ARTICLE{e83-a_2_267,
author={Hyuk-Jun SUNG, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm},
year={2000},
volume={E83-A},
number={2},
pages={267-271},
abstract={This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 267
EP - 271
AU - Hyuk-Jun SUNG
AU - Kwang Sub YOON
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.
ER -
English
