In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

A novel linear voltage-to-current conversion circuit for a rail-to-rail input voltage is proposed in this paper. A pair of MOSFETs operating in plural regions are used for the conversion and a difference of their drain currents is used as an output current. The two MOSFETs work complemetarily and realize a rail-to-rail input range. The output current is linear in any input voltage from the ground potential to a power-supply voltage. Two types of circuit configurations which realize the proposed concept are given. From the viewpoint of area efficiency and linearity the proposed circuit is superior to a voltage-to-current converter previously proposed by the authors, which uses a set of three MOSFETs to achieve a rail-to-rail voltage-to-current conversion . The operation principle of the proposed method is confirmed through HSPICE simulations.

This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.

In this paper we introduce a CMOS low voltage/low power (LV/LP) voltage controlled oscillator (VCO). It includes a simple V-I converter, a current controlled ring oscillator based on new differential delay cells, and a source-coupled differential pair to convert differential signal to single-ended signal. The V-I converter is implemented as a source follower type, exhibiting excellent linearity of transconductance with low power consumption. The new delay cell employs local positive feedback to increase its DC gain, achieving stable oscillation at low supply voltage. The simulation and measurement results are given to show the linearity between the input (control voltage) and the output (frequency) in the frequency range of 100 MHz to 400 MHz with 1. 2 V power supply. The VCO only consumes power of 2.25 mW at operating frequency of 400 MHz and 1.2 V supply.