IEICE TRANSACTIONS on Fundamentals
VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
Summary :
Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2697-2704
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Layout
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, "VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2697-2704, November 2001, doi: .
Abstract: Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2697/_p
Copy
@ARTICLE{e84-a_11_2697,
author={Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation},
year={2001},
volume={E84-A},
number={11},
pages={2697-2704},
abstract={Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2697
EP - 2704
AU - Yuchun MA
AU - Xianlong HONG
AU - Sheqin DONG
AU - Yici CAI
AU - Chung-Kuan CHENG
AU - Jun GU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
ER -
English
