A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers
Summary :
A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.2 pp.563-567
- Publication Date
- 2001/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hyung Hoon KIM, Kwang Sub YOON, "A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 2, pp. 563-567, February 2001, doi: .
Abstract: A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_2_563/_p
Copy
@ARTICLE{e84-a_2_563,
author={Hyung Hoon KIM, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers},
year={2001},
volume={E84-A},
number={2},
pages={563-567},
abstract={A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 563
EP - 567
AU - Hyung Hoon KIM
AU - Kwang Sub YOON
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2001
AB - A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
ER -
English
