IEICE TRANSACTIONS on Fundamentals
Statistical Gate-Delay Modeling with Intra-Gate Variability
Summary :
This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.2914-2922
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Parasitics and Noise
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kenichi OKADA, Kento YAMAOKA, Hidetoshi ONODERA, "Statistical Gate-Delay Modeling with Intra-Gate Variability" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 2914-2922, December 2003, doi: .
Abstract: This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_2914/_p
Copy
@ARTICLE{e86-a_12_2914,
author={Kenichi OKADA, Kento YAMAOKA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Statistical Gate-Delay Modeling with Intra-Gate Variability},
year={2003},
volume={E86-A},
number={12},
pages={2914-2922},
abstract={This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Statistical Gate-Delay Modeling with Intra-Gate Variability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2914
EP - 2922
AU - Kenichi OKADA
AU - Kento YAMAOKA
AU - Hidetoshi ONODERA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.
ER -
English
