IEICE TRANSACTIONS on Fundamentals
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
Summary :
A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.4 pp.841-845
- Publication Date
- 2003/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
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Atsushi KUROKAWA, Kotaro HACHIYA, Takashi SATO, Kazuya TOKUMASU, Hiroo MASUDA, "Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 4, pp. 841-845, April 2003, doi: .
Abstract: A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_4_841/_p
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@ARTICLE{e86-a_4_841,
author={Atsushi KUROKAWA, Kotaro HACHIYA, Takashi SATO, Kazuya TOKUMASU, Hiroo MASUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects},
year={2003},
volume={E86-A},
number={4},
pages={841-845},
abstract={A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 841
EP - 845
AU - Atsushi KUROKAWA
AU - Kotaro HACHIYA
AU - Takashi SATO
AU - Kazuya TOKUMASU
AU - Hiroo MASUDA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2003
AB - A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.
ER -
English
