An ESL-cancelling circuit for a shunt-connected film capacitor filter using vertically stacked coupled square loops is reported in this paper. The circuit is applicable for a shunt-connected capacitor filter whose equivalent series inductance (ESL) of the shunt-path causes deterioration of filter performance at frequencies above the self-resonant frequency. Two pairs of vertically stacked magnetically coupled square loops are used in the circuit those can equivalently add negative inductance in series to the shunt-path to cancel ESL for improvement of the filter performance. The ESL-cancelling circuit for a 1-μF film capacitor was designed according to the Biot-Savart law and electromagnetic (EM)-analysis, and the prototype was fabricated with an FR4 substrate. The measured result showed 20-dB improvement of the filter performance above the self-resonant frequency as designed, satisfying Sdd21 less than -40dB at 1MHz to 100MHz. This result is almost equivalent to reduce ESL of the shunt-path to less than 1nH at 100MHz and is also difficult to realize using any kind of a single bulky film capacitor without cancelling ESL.

In this paper, the author performed an electromagnetic field simulation of a typical bonding wire structure that connects a chip and a package, and evaluated the signal transmission characteristics (S-parameters). In addition, the inductance per unit length was extracted by comparing with the equivalent circuit of the distributed constant line. It turns out that the distributed constant line model is not sufficient because there are frequencies where chip-package resonance occurs. Below the resonance frequency, the conventional low-frequency approximation model was effective, and it was found that the inductance was about 1nH/mm.

Superconducting detectors have been shown to be superior to other techniques in some applications. However, superconducting devices have not been used for detecting neutrons often in the past decades. We have been developing various superconducting neutron detectors. In this paper, we review our attempts to measure neutrons using superconducting stripline detectors with DC bias currents. These include attempts with a MgB2-based detector and a Nb-based detector with a 10B converter.

A lumped element kinetic inductance detector (LeKID) relying on a superconducting resonator is a promising candidate for sensing high energy particles such as neutrinos, X-rays, gamma-rays, alpha particles, and the particles found in the dark matter owing to its large-format capability and high sensitivity. To develop a high energy camera, we formulated design rules based on the experimental results from niobium (Nb)-based LeKIDs at 1 K irradiated with alpha-particles of 5.49 MeV. We defined the design rules using the electromagnetic simulations for minimizing the crosstalk. The neighboring pixels were fixed at 150 µm with a frequency separation of 250 MHz from each other to reduce the crosstalk signal as low as the amplifier-limited noise level. We examined the characteristics of the Nb-based resonators, where the signal decay time was controlled in the range of 0.5-50 µs by changing the designed quality factor of the detectors. The amplifier noise was observed to restrict the performance of our device, as expected. We improved the energy resolution by reducing the filling factor of inductor lines. The best energy resolution of 26 for the alpha particle of 5.49 MeV was observed in our device.

In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.

Antenna-coupled kinetic inductance detectors (KIDs) have recently shown great promise as microwave detection systems with a large number of channels. However, this technique, still has difficulties in eliminating the radiation loss of the resonator signals. To solve this problem, we propose a design in which the absorption area connected to an antenna is located on the ground-side of a coplanar waveguide. Thereby, radiation loss due to leakage from the resonator to the antenna can be considerably reduced. This simple design also enables the use of a contact aligner for fabrication. We have developed KIDs with this design, named as the ground-side absorption (GSA)-KIDs and demonstrated that they have higher quality factors than those of the existing KIDs, while maintaining a good total sensitivity.

Near field communication (NFC) antennas are often lined with magnetic sheets to reduce performance degradation caused by nearby metal objects. Though amorphous sheets have a high permeability and are suitable magnetic sheets for lining, their magnetic loss is also high. Therefore, this paper suggests a technique of suppressing magnetic loss by modifying the shape of the sheet without changing its composition. The utility of the proposed technique was investigated in this study.

We describe a calculation tool and modeling methods to find self and mutual inductance and current distribution in superconductive multilayer circuit layouts. Accuracy of the numerical solver is discussed and compared with experimental measurements. Effects of modeling parameter selection on calculation results are shown, and we make conclusions on the selection of modeling parameters for fast but sufficiently accurate calculations when calibration methods are used. Circuit theory for the calculation of branch impedances from the output of the numerical solver is discussed, and compensation for solution difficulties is shown through example. We elaborate on the construction of extraction models for superconductive integrated circuits, with and without resistive branches. We also propose a method to calculate current distribution in a multilayer circuit with multiple bias current feed points. Finally, detailed examples are shown where the effects of stacked vias, bias pillars, coupling, ground connection stacks and ground return currents in circuit layouts for the AIST advanced process (ADP2) and standard process (STP2) are analyzed. We show that multilayer inductance and current distribution extraction in such circuits provides much more information than merely branch inductance, and can be used to improve layouts; for example through reduced coupling between conductors.

One of the fundamental problems in many-pixel detectors implemented in cryogenics environments is the number of bias and read-out wires. If one targets a megapixel range detector, number of wires should be significantly reduced. One possibility is that the detectors are serially connected and biased by using only one line and read-out is accomplished by on-chip circuitry. In addition to the number of pixels, the detectors should have fast response times, low dead times, high sensitivities, low inter-pixel crosstalk and ability to respond to simultaneous irradiations to individual pixels for practical purposes. We have developed an equivalent circuit model for a serially connected superconducting strip line detector (SSLD) array together with the read-out electronics. In the model we take into account the capacitive effects due to the ground plane under the detector, effects of the shunt resistors fabricated under the SSLD layer, low pass filters placed between the individual pixels that enable individual operation of each pixel and series resistors that prevents the DC bias current flowing to the read-out electronics as well as adjust the time constants of the inductive SSLD loop. We explain the results of investigation of the following parameters: Crosstalk between the neighbor pixels, response to simultaneous irradiation, dead times, L/R time constants, low pass filters, and integration with the SFQ front-end circuit. Based on the simulation results, we show that SSLDs are promising devices for detecting a wide range of incident radiation such as neurons, X-rays and THz waves in many-pixel configurations.

Fast simulation techniques of large scale RLC networks with nonlinear devices are presented. Generally, when scale of nonlinear part in a circuit is much less than the linear part, matrix or circuit partitioning approach is known to be efficient. In this paper, these partitioning techniques are used for the conventional transient analysis using an implicit numerical integration and the circuit-based finite-difference time-domain (FDTD) method, whose efficiency and accuracy are evaluated developing a prototype simulator. It is confirmed that the matrix and circuit partitioning approaches do not degrade accuracy of the transient simulations that is compatible to SPICE, and that the circuit partitioning approach is superior to the matrix one in efficiency. Moreover, it is demonstrated that the circuit-based FDTD method can be efficiently combined with the matrix or circuit partitioning approach, compared with the transient analysis using an implicit numerical integration.

In this paper, several spiral inductors with various ground clearance structures and turns were investigated to achieve noise suppression up to the fourth harmonic (3.2 GHz) regime of DDR3-1600. Their performances were characterized in terms of their capability to effectively suppress simultaneous switching noise (SSN) in the frequency region of interest. For a wider noise suppression bandwidth, a spiral inductor with large ground clearance, which provides a high self resonance frequency (SRF) as well as high inductances, was implemented. The proposed spiral inductor exhibited good noise suppression characteristics in the frequency domain and achieved 50% voltage fluctuation reduction in the time domain, compared to the identical 4-turn spiral without pattern ground structure.

This paper presents a high-efficiency boost converter with voltage clamp function. It clarifies how to design the inductance of the coupled inductor used in the converter, and derives characteristic equations that associate the fluctuation in the input voltage with the output ripple current. For this converter, a theoretical analysis, simulation and experimentation (prototype output: 98 V, 13 A) are performed. As a result, the converter is achieved high efficiency (Maximum efficiency: 98.1%) in the rated output condition, indicating that the voltage stress on the switching power semiconductors can be mitigated by using the voltage clamp function. And it is verified that the snubber circuit can be eliminated in the switching power semiconductors. In addition, the theoretical output ripple current characteristics are corresponded well with simulation and experimental results, and the validity of the design method is proved.

A loosened connector between interconnected electric devices causes an increase in electromagnetic radiation when the devices operate in high-frequency bands. To develop a high-frequency circuit equivalent to a connector with contact failure, we previously investigated the parasitic elements caused by failure at the contact boundary. From the results of that study, the inductance and resistance at a connection contact boundary are increased by the loosening of a connector. Furthermore, the increase in inductance is the dominant factor in increasing the intensity of the electromagnetic radiation. In this paper, to suppress electromagnetic radiation resulting from a loose contact, we formulate the contact performance requirement needed to maintain a good contact condition when a small loosening has occurred at the interconnection. To this end, we investigate the mechanism of increase in the inductance by loosening the connector.

We present analytical expression for inductance of a superconducting stripline, a strip sandwiched by two superconducting ground planes. In our method, we utilize the analytical formula for a perfect-conducting stripline derived by Chang in 1976. To utilize Chang's formula, we first transform the structure of a superconducting stripline into that of a perfect-conducting stripline by reducing the thicknesses of the superconducting layers. The thickness reduction is "λ coth (t/λ)" for each (upper or lower) side, where λ and t are the field penetration depth and the layer thickness, respectively. Then, we apply Chang's formula to the transformed stripline model. The calculated results are in good agreement with the numerical and experimental results.

This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. To generate the sparse reluctance matrix with guaranteed stability, the original matrix has to be (strictly) diagonally dominant M matrix. Hence, the repeated inductance extractions with a smaller grid size are necessary in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix. These ease the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using double inverse methods. Since reluctance components are not still supported in SPICE-like simulators, generating the sparse inductance matrix is more useful than the sparse reluctance one.

A physics-based equivalent circuit model of the ceramic capacitor is proposed, which can reproduce frequency characteristics of its impedance including the often observed yet hitherto physically unexplained kinks appearing above the primary series resonance frequency. The model can also account for parasitic effects of external inductances. In order to efficiently analyze and gain engineering insight into ceramic capacitors with a large number of metallic laminae, a two-dimensional method of moments is developed that treats the laminar structure as a uniform, effective medium. It turns out that the primary resonance and the kinks can be well understood and modeled by a lossy transmission line stub with a drastic wavelength reduction. The capacitor model is completed by adding components describing the skin effect and external inductances. The modeled impedance stays within a 4% margin of error up to 5 GHz. The proposed model could greatly improve the accuracy of power distribution network simulation.

Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.

Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.

NEXT (Near End Crosstalk loss) and FEXT (Far End Crosstalk loss) of a high speed LAN connector are analyzed using a simple coupled line model and examined experimentally. "Crosstalk Chart" is also proposed, by which, the NEXT and FEXT can be easily read off from the mutual inductance and unbalanced capacitance between pair of lines. This approach is effective for Cat.5e [1] connectors. However, for Cat.6 [2], of which transmission bandwidth is widen to 250 MHz, some additional adjustments of path pattern on the jack and terminals PCB are required. In order to assist such the adjustments, a new simple measurement technique to grasp the complex crosstalk characteristics is proposed. Two examples are introduced. One is a conventional telephone rosette, which is enhanced to be co-usable for a Cat.5e LAN connector, where only its original circuit board is reengineered. Another is a Cat.6 connector of which PCB is modified from a conventional Cat.5e connector.

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.