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IEICE TRANSACTIONS on Fundamentals

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design

Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, Masanori HASHIMOTO

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Summary :

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3560-3568
Publication Date
2006/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1093/ietfec/e89-a.12.3560
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Interconnect

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