IEICE TRANSACTIONS on Fundamentals
Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's
Summary :
In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.7 pp.1759-1765
- Publication Date
- 2003/07/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Analog Signal Processing
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Dasong ZHU, Koichi TANNO, Okihiko ISHIZUKA, "Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 7, pp. 1759-1765, July 2003, doi: .
Abstract: In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_7_1759/_p
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@ARTICLE{e86-a_7_1759,
author={Dasong ZHU, Koichi TANNO, Okihiko ISHIZUKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's},
year={2003},
volume={E86-A},
number={7},
pages={1759-1765},
abstract={In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1759
EP - 1765
AU - Dasong ZHU
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2003
AB - In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.
ER -
English
