IEICE TRANSACTIONS on Fundamentals
A Realization of Multiple-Output Functions by a Look-Up Table Ring
Summary :
A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 µm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3141-3150
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
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Hui QIN, Tsutomu SASAO, Munehiro MATSUURA, Shinobu NAGAYAMA, Kazuyuki NAKAMURA, Yukihiro IGUCHI, "A Realization of Multiple-Output Functions by a Look-Up Table Ring" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3141-3150, December 2004, doi: .
Abstract: A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 µm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3141/_p
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@ARTICLE{e87-a_12_3141,
author={Hui QIN, Tsutomu SASAO, Munehiro MATSUURA, Shinobu NAGAYAMA, Kazuyuki NAKAMURA, Yukihiro IGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Realization of Multiple-Output Functions by a Look-Up Table Ring},
year={2004},
volume={E87-A},
number={12},
pages={3141-3150},
abstract={A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 µm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Realization of Multiple-Output Functions by a Look-Up Table Ring
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3141
EP - 3150
AU - Hui QIN
AU - Tsutomu SASAO
AU - Munehiro MATSUURA
AU - Shinobu NAGAYAMA
AU - Kazuyuki NAKAMURA
AU - Yukihiro IGUCHI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 µm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.
ER -
English
