Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA

Yuya MATSUMOTO; Yuichi TANJI; Mamoru TANAKA

Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA

Yuya MATSUMOTO, Yuichi TANJI, Mamoru TANAKA

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This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.1 pp.251-257

Publication Date: 2004/01/01

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Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Yuya MATSUMOTO, Yuichi TANJI, Mamoru TANAKA, "Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 1, pp. 251-257, January 2004, doi: .
Abstract: This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_1_251/_p

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@ARTICLE{e87-a_1_251,
author={Yuya MATSUMOTO, Yuichi TANJI, Mamoru TANAKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA},
year={2004},
volume={E87-A},
number={1},
pages={251-257},
abstract={This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 251
EP - 257
AU - Yuya MATSUMOTO
AU - Yuichi TANJI
AU - Mamoru TANAKA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2004
AB - This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.
ER -