Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage

Masayuki ARAI; Kazuhiko IWASAKI

doi:10.1587/transfun.E100.A.1488

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage

Masayuki ARAI, Kazuhiko IWASAKI

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Shrinking feature sizes and higher levels of integration in semiconductor device manufacturing technologies are increasingly causing the gap between defect levels estimated in the design stage and reported ones for fabricated devices. In this paper, we propose a unified weighted fault coverage approach that includes both bridge and open faults, considering the critical area as the incident rate of each fault. We then propose a test pattern reordering scheme that incorporates our weighted fault coverage with an aim to reduce test costs. Here we apply a greedy algorithm to reorder test patterns generated by the bridge and stuck-at automatic test pattern generator (ATPG), evaluating the relationship between the number of patterns and the weighted fault coverage. Experimental results show that by applying this reordering scheme, the number of test patterns was reduced, on average, by approximately 50%. Our results also indicate that relaxing coverage constraints can drastically reduce test pattern set sizes to a level comparable to traditional 100% coverage stuck-at pattern sets, while targeting the majority of bridge faults and keeping the defect level to no more than 10 defective parts per milion (DPPM) with a 99% manufacturing yield.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.7 pp.1488-1495

Publication Date: 2017/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.1488

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Masayuki ARAI
Nihon University
Kazuhiko IWASAKI
Tokyo Metropolitan University

Keyword

weighted fault coverage, critical area, test cost reduction, test pattern reduction, bridge fault, open fault

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Masayuki ARAI, Kazuhiko IWASAKI, "Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 7, pp. 1488-1495, July 2017, doi: 10.1587/transfun.E100.A.1488.
Abstract: Shrinking feature sizes and higher levels of integration in semiconductor device manufacturing technologies are increasingly causing the gap between defect levels estimated in the design stage and reported ones for fabricated devices. In this paper, we propose a unified weighted fault coverage approach that includes both bridge and open faults, considering the critical area as the incident rate of each fault. We then propose a test pattern reordering scheme that incorporates our weighted fault coverage with an aim to reduce test costs. Here we apply a greedy algorithm to reorder test patterns generated by the bridge and stuck-at automatic test pattern generator (ATPG), evaluating the relationship between the number of patterns and the weighted fault coverage. Experimental results show that by applying this reordering scheme, the number of test patterns was reduced, on average, by approximately 50%. Our results also indicate that relaxing coverage constraints can drastically reduce test pattern set sizes to a level comparable to traditional 100% coverage stuck-at pattern sets, while targeting the majority of bridge faults and keeping the defect level to no more than 10 defective parts per milion (DPPM) with a 99% manufacturing yield.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.1488/_p

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@ARTICLE{e100-a_7_1488,
author={Masayuki ARAI, Kazuhiko IWASAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage},
year={2017},
volume={E100-A},
number={7},
pages={1488-1495},
abstract={Shrinking feature sizes and higher levels of integration in semiconductor device manufacturing technologies are increasingly causing the gap between defect levels estimated in the design stage and reported ones for fabricated devices. In this paper, we propose a unified weighted fault coverage approach that includes both bridge and open faults, considering the critical area as the incident rate of each fault. We then propose a test pattern reordering scheme that incorporates our weighted fault coverage with an aim to reduce test costs. Here we apply a greedy algorithm to reorder test patterns generated by the bridge and stuck-at automatic test pattern generator (ATPG), evaluating the relationship between the number of patterns and the weighted fault coverage. Experimental results show that by applying this reordering scheme, the number of test patterns was reduced, on average, by approximately 50%. Our results also indicate that relaxing coverage constraints can drastically reduce test pattern set sizes to a level comparable to traditional 100% coverage stuck-at pattern sets, while targeting the majority of bridge faults and keeping the defect level to no more than 10 defective parts per milion (DPPM) with a 99% manufacturing yield.},
keywords={},
doi={10.1587/transfun.E100.A.1488},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1488
EP - 1495
AU - Masayuki ARAI
AU - Kazuhiko IWASAKI
PY - 2017
DO - 10.1587/transfun.E100.A.1488
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2017
AB - Shrinking feature sizes and higher levels of integration in semiconductor device manufacturing technologies are increasingly causing the gap between defect levels estimated in the design stage and reported ones for fabricated devices. In this paper, we propose a unified weighted fault coverage approach that includes both bridge and open faults, considering the critical area as the incident rate of each fault. We then propose a test pattern reordering scheme that incorporates our weighted fault coverage with an aim to reduce test costs. Here we apply a greedy algorithm to reorder test patterns generated by the bridge and stuck-at automatic test pattern generator (ATPG), evaluating the relationship between the number of patterns and the weighted fault coverage. Experimental results show that by applying this reordering scheme, the number of test patterns was reduced, on average, by approximately 50%. Our results also indicate that relaxing coverage constraints can drastically reduce test pattern set sizes to a level comparable to traditional 100% coverage stuck-at pattern sets, while targeting the majority of bridge faults and keeping the defect level to no more than 10 defective parts per milion (DPPM) with a 99% manufacturing yield.
ER -