A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Summary :
Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.7 pp.1496-1499
- Publication Date
- 2017/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E100.A.1496
- Type of Manuscript
- Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Takahiro YAMAMOTO
Ritsumeikan University
Ittetsu TANIGUCHI
Ritsumeikan University
Hiroyuki TOMIYAMA
Ritsumeikan University
Shigeru YAMASHITA
Ritsumeikan University
Yuko HARA-AZUMI
Tokyo Institute of Technology
Keyword
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Takahiro YAMAMOTO, Ittetsu TANIGUCHI, Hiroyuki TOMIYAMA, Shigeru YAMASHITA, Yuko HARA-AZUMI, "A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers" in IEICE TRANSACTIONS on Fundamentals,
vol. E100-A, no. 7, pp. 1496-1499, July 2017, doi: 10.1587/transfun.E100.A.1496.
Abstract: Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.1496/_p
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@ARTICLE{e100-a_7_1496,
author={Takahiro YAMAMOTO, Ittetsu TANIGUCHI, Hiroyuki TOMIYAMA, Shigeru YAMASHITA, Yuko HARA-AZUMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers},
year={2017},
volume={E100-A},
number={7},
pages={1496-1499},
abstract={Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.},
keywords={},
doi={10.1587/transfun.E100.A.1496},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1496
EP - 1499
AU - Takahiro YAMAMOTO
AU - Ittetsu TANIGUCHI
AU - Hiroyuki TOMIYAMA
AU - Shigeru YAMASHITA
AU - Yuko HARA-AZUMI
PY - 2017
DO - 10.1587/transfun.E100.A.1496
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2017
AB - Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.
ER -
English
