IEICE TRANSACTIONS on Fundamentals
Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits
Summary :
Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.4 pp.1031-1038
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1031
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
- Category
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Shiho HAGIWARA, Takashi SATO, Kazuya MASU, "Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1031-1038, April 2009, doi: 10.1587/transfun.E92.A.1031.
Abstract: Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1031/_p
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@ARTICLE{e92-a_4_1031,
author={Shiho HAGIWARA, Takashi SATO, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits},
year={2009},
volume={E92-A},
number={4},
pages={1031-1038},
abstract={Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.},
keywords={},
doi={10.1587/transfun.E92.A.1031},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1031
EP - 1038
AU - Shiho HAGIWARA
AU - Takashi SATO
AU - Kazuya MASU
PY - 2009
DO - 10.1587/transfun.E92.A.1031
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.
ER -
English
