Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Summary :
Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3094-3102
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3094
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verfication
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Hiroshi FUKETA, Masanori HASHIMOTO, Yukio MITSUYAMA, Takao ONOYE, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3094-3102, December 2009, doi: 10.1587/transfun.E92.A.3094.
Abstract: Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3094/_p
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@ARTICLE{e92-a_12_3094,
author={Hiroshi FUKETA, Masanori HASHIMOTO, Yukio MITSUYAMA, Takao ONOYE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction},
year={2009},
volume={E92-A},
number={12},
pages={3094-3102},
abstract={Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.},
keywords={},
doi={10.1587/transfun.E92.A.3094},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3094
EP - 3102
AU - Hiroshi FUKETA
AU - Masanori HASHIMOTO
AU - Yukio MITSUYAMA
AU - Takao ONOYE
PY - 2009
DO - 10.1587/transfun.E92.A.3094
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.
ER -
English
