Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Summary :
This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3103-3110
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3103
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verfication
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Qing DONG, Bo YANG, Jing LI, Shigetoshi NAKATAKE, "Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3103-3110, December 2009, doi: 10.1587/transfun.E92.A.3103.
Abstract: This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3103/_p
Copy
@ARTICLE{e92-a_12_3103,
author={Qing DONG, Bo YANG, Jing LI, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming},
year={2009},
volume={E92-A},
number={12},
pages={3103-3110},
abstract={This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.},
keywords={},
doi={10.1587/transfun.E92.A.3103},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3103
EP - 3110
AU - Qing DONG
AU - Bo YANG
AU - Jing LI
AU - Shigetoshi NAKATAKE
PY - 2009
DO - 10.1587/transfun.E92.A.3103
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.
ER -
English
