IEICE TRANSACTIONS on Fundamentals
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System
Summary :
Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.389-400
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.389
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
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Shu-Yu JIANG, Chan-Wei HUANG, Yu-Lung LO, Kuo-Hsing CHENG, "Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 389-400, February 2009, doi: 10.1587/transfun.E92.A.389.
Abstract: Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.389/_p
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@ARTICLE{e92-a_2_389,
author={Shu-Yu JIANG, Chan-Wei HUANG, Yu-Lung LO, Kuo-Hsing CHENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System},
year={2009},
volume={E92-A},
number={2},
pages={389-400},
abstract={Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.},
keywords={},
doi={10.1587/transfun.E92.A.389},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 389
EP - 400
AU - Shu-Yu JIANG
AU - Chan-Wei HUANG
AU - Yu-Lung LO
AU - Kuo-Hsing CHENG
PY - 2009
DO - 10.1587/transfun.E92.A.389
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.
ER -
English
