This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.