A Fast-Lock DLL with Power-On Reset Circuit

Kuo-Hsing CHENG; Yu-Lung LO; Shu-Yu JIANG

A Fast-Lock DLL with Power-On Reset Circuit

Kuo-Hsing CHENG, Yu-Lung LO, Shu-Yu JIANG

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This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.9 pp.2210-2220

Publication Date: 2004/09/01

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Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications)

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Kuo-Hsing CHENG, Yu-Lung LO, Shu-Yu JIANG, "A Fast-Lock DLL with Power-On Reset Circuit" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 9, pp. 2210-2220, September 2004, doi: .
Abstract: This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_9_2210/_p

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@ARTICLE{e87-a_9_2210,
author={Kuo-Hsing CHENG, Yu-Lung LO, Shu-Yu JIANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast-Lock DLL with Power-On Reset Circuit},
year={2004},
volume={E87-A},
number={9},
pages={2210-2220},
abstract={This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - A Fast-Lock DLL with Power-On Reset Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2210
EP - 2220
AU - Kuo-Hsing CHENG
AU - Yu-Lung LO
AU - Shu-Yu JIANG
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2004
AB - This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.
ER -