This paper describes a fast-lock delay-lock loop (DLL) with a power-on reset (POR) circuit. A novel POR circuit and coarse tune (CT) circuit are used to overcome the false locking problems associated with conventional DLL's and offer a faster locking time. The CT circuit is used to control the DLL loop bandwidth to reduce the locking time while maintaining stability and better jitter performance. Moreover, a new voltage-controlled delay line is proposed to reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on the TSMC 0.35 µm single-poly four-metal CMOS process. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequencies are 100 MHz and 190 MHz, the measured output clock rms jitter are 12.44 ps and 8.463 ps, respectively. Furthermore, the locking time is less than 43 clock cycles based on the HSPICE simulation results.