IEICE TRANSACTIONS on Fundamentals
A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
Summary :
A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.2 pp.395-401
- Publication Date
- 2010/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.395
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
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Tomohiko ITO, Tetsuro ITAKURA, "A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 395-401, February 2010, doi: 10.1587/transfun.E93.A.395.
Abstract: A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.395/_p
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@ARTICLE{e93-a_2_395,
author={Tomohiko ITO, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers},
year={2010},
volume={E93-A},
number={2},
pages={395-401},
abstract={A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.},
keywords={},
doi={10.1587/transfun.E93.A.395},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 395
EP - 401
AU - Tomohiko ITO
AU - Tetsuro ITAKURA
PY - 2010
DO - 10.1587/transfun.E93.A.395
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.
ER -
English
