The 5th-generation mobile communication uses multi-element array antennas in not only base stations but also mobile terminals. In order to design multi-element array antennas efficiently, it is important to acquire the characteristics of the direction of arrival (DOA) and direction of departure (DOD), and a highly accurate and simple measurement method is required. This paper proposes a highly accurate and simple method to measure DOA and DOD by applying synthetic aperture (SA) processed at both Rx and Tx sides. It is also shown that the addition of beam scanning to the proposed method can reduce the measurement time while maintaining the peak detection resolution. Moreover, experiments in an anechoic chamber and a shielded room using actual wave sources confirm that DOA and DOD can be detected with high accuracy.

This paper proposes and characterizes an A/D converter (ADC) based on a spiking neuron model with a rectangular threshold signal. The neuron repeats an integrate-and-fire process and outputs a superstable spike sequence. The dynamics of this system are closely related to those of rate-encoding ADCs. We propose an ADC system based on the spiking neuron model. We derive a theoretical parameter region in a limited time interval of the digital output sequence. We analyze the conversion characteristics in this region and verify that they retain the monotonic increase and rate encoding of an ADC.

This paper proposes a method for cooperative multi-static Multiple Input Multiple Output (MIMO) radar that can estimate the number of targets. The purpose of this system is to monitor humans in an indoor environment. First, target positions within the estimation range are roughly detected by the Capon method and the mode vector corresponding to the detected positions is calculated. The mode vector is multiplied by the eigenvector to eliminate the virtual image. The spectrum of the evaluation function is calculated from the remaining positions, and the number of peaks in the spectrum is defined as the number of targets. Experiments carried out in an indoor environment confirm that the proposed method can estimate the number of targets with high accuracy.

Applications of continuous-time (CT) comparator include relaxation oscillators, pulse width modulators, and so on. CT comparator receives a differential input and outputs a strobe ideally when the differential input crosses zero. Unlike the DT comparators with positive feedback circuit, amplifiers consuming static power must be employed in CT comparators to amplify the input signal. Therefore, minimization of comparator delay under the constraint of power consumption often becomes an issue. This paper analyzes transient behavior of a CT comparator. Using “constant delay approximation”, the comparator delay is derived as a function of input slew rate, number of stages of the preamplifier, and device parameters in each block. This paper also discusses optimum design of the CT comparator. The condition for minimum comparator delay is derived with keeping power consumption constant. The results include that the optimum DC gain of the preamplifier is e∼e3 per stage depending on the element which dominates load capacitance of the preamplifier.

A feedforward (FF) network using ΔΣ modulators is investigated to implement a non-binary analog-to-digital (A/D) converter. Weighting coefficients in the network are determined to suppress the generation of quantization noise. A moving average is adopted to prevent the analog signal amplitude from increasing beyond the allowable input range of the modulators. The noise transfer function is derived and used to estimate the signal-to-noise ratio (SNR). The FF network output is a non-uniformly distributed multi-level signal, which results in a better SNR than a uniformly distributed one. Also, the effect of the characteristic mismatch in analog components on the SNR is analyzed. Our behavioral simulations show that the SNR is improved by more than 30 dB, or equivalently a bit resolution of 5 bits, compared with a conventional first-order ΔΣ modulator.

This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.

In the present paper, we propose a novel high-resolution analog-to-digital converter (ADC) for low-power biomedical analog front-ends, which we call the successive stochastic approximation ADC. The proposed ADC uses a stochastic flash ADC (SF-ADC) to realize a digitally controlled variable-threshold comparator in a successive-approximation-register ADC (SAR-ADC), which can correct errors originating from the internal digital-to-analog converter in the SAR-ADC. For the residual error after SAR-ADC operation, which can be smaller than thermal noise, the SF-ADC uses the statistical characteristics of noise to achieve high resolution. The SF-ADC output for the residual signal is combined with the SAR-ADC output to obtain high-precision output data using the supervised machine learning method.

This letter presents a new time-digital single-slope ADC (TDSS) architecture for CMOS image sensors. In the proposed ADC, a conventional single-slope ADC is used in coarse phase and a time to digital convertor is employed in fine phase. Through second comparison of the two different slope voltages (discharge input voltage and ramp voltage), the proposed ADC achieves low bit precision compensation. Compared with multiple-ramp single-slope (MRSS) ADC, the proposed ADC not only has a simple digital judgment circuit, but also increases conversion speed without complicated structure of ramp generator. A 10-bit TDSS ADC consisting of 7-bit conventional single-slope ADC and 3-bit time to digital converter was realized in a 0.13µm CIS process. Simulations demonstrate that the conversion speed of a TDSS ADC is almost 3.5 times faster than that of a single-slope ADC.

We report a trial of 100-GS/s optical quantization with 5-bit resolution using soliton self-frequency shift (SSFS) and spectral compression. We confirm that 100-GS/s 5-bit optical quantization is realized to quantize a 5.0-GHz sinusoid electrical signal in simulation. In order to experimentally verify the possibility of 100-GS/s 5-bit optical quantization, we execute 5-bit optical quantization by using two sampled signals with 10-ps intervals.

In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm2 and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 65 µm2 and consumes 380 µW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.

A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.

This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.

A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.

Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 µm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.