IEICE TRANSACTIONS on Fundamentals
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
Summary :
The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2456-2462
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2456
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Xiaolei ZHU
Yanfei CHEN
Masaya KIBUNE
Yasumoto TOMITA
Takayuki HAMADA
Hirotaka TAMURA
Sanroku TSUKAMOTO
Tadahiro KURODA
Keyword
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Xiaolei ZHU, Yanfei CHEN, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Hirotaka TAMURA, Sanroku TSUKAMOTO, Tadahiro KURODA, "A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2456-2462, December 2010, doi: 10.1587/transfun.E93.A.2456.
Abstract: The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2456/_p
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@ARTICLE{e93-a_12_2456,
author={Xiaolei ZHU, Yanfei CHEN, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Hirotaka TAMURA, Sanroku TSUKAMOTO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology},
year={2010},
volume={E93-A},
number={12},
pages={2456-2462},
abstract={The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
keywords={},
doi={10.1587/transfun.E93.A.2456},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2456
EP - 2462
AU - Xiaolei ZHU
AU - Yanfei CHEN
AU - Masaya KIBUNE
AU - Yasumoto TOMITA
AU - Takayuki HAMADA
AU - Hirotaka TAMURA
AU - Sanroku TSUKAMOTO
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transfun.E93.A.2456
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25
ER -
English
