IEICE TRANSACTIONS on Fundamentals
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Summary :
For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.4 pp.1067-1081
- Publication Date
- 2011/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.1067
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, "Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 4, pp. 1067-1081, April 2011, doi: 10.1587/transfun.E94.A.1067.
Abstract: For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1067/_p
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@ARTICLE{e94-a_4_1067,
author={Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis},
year={2011},
volume={E94-A},
number={4},
pages={1067-1081},
abstract={For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.},
keywords={},
doi={10.1587/transfun.E94.A.1067},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1067
EP - 1081
AU - Keisuke INOUE
AU - Mineo KANEKO
AU - Tsuyoshi IWAGAKI
PY - 2011
DO - 10.1587/transfun.E94.A.1067
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2011
AB - For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.
ER -
English
