IEICE TRANSACTIONS on Fundamentals
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
Summary :
Due to the increased power density and lower thermal conductivity, 3D ICs are faced with heat dissipation and temperature problem seriously. TSV (Through-Silicon-Via) has been shown as an effective way to help heat removal, but they introduce several issues related with cost and reliability as well. Previous researches of TSV planning didn't pay much attention to the impact of leakage power, which will bring in error on estimation of temperature, TSV number and also critical path delay. The leakage-temperature-delay dependence can potentially negate the performance improvement of 3D designs. In this paper, we analyze the impact of leakage power on TSV planning and integrate leakage-temperature-delay dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering the influence on both module delay and wire delay, is proposed to achieve the best balance among temperature, via number and performance. Experiment results show that, with leakage power and resource constraint considered, temperature and the required via number can be quite different, and the weighted TSV insertion approach with iterative process can obtain the trade-off between different factors including thermal, power consumption, via number and performance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2490-2498
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2490
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Level Design
Authors
Keyword
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Kan WANG, Sheqin DONG, Yuchun MA, Yu WANG, Xianlong HONG, Jason CONG, "Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2490-2498, December 2011, doi: 10.1587/transfun.E94.A.2490.
Abstract: Due to the increased power density and lower thermal conductivity, 3D ICs are faced with heat dissipation and temperature problem seriously. TSV (Through-Silicon-Via) has been shown as an effective way to help heat removal, but they introduce several issues related with cost and reliability as well. Previous researches of TSV planning didn't pay much attention to the impact of leakage power, which will bring in error on estimation of temperature, TSV number and also critical path delay. The leakage-temperature-delay dependence can potentially negate the performance improvement of 3D designs. In this paper, we analyze the impact of leakage power on TSV planning and integrate leakage-temperature-delay dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering the influence on both module delay and wire delay, is proposed to achieve the best balance among temperature, via number and performance. Experiment results show that, with leakage power and resource constraint considered, temperature and the required via number can be quite different, and the weighted TSV insertion approach with iterative process can obtain the trade-off between different factors including thermal, power consumption, via number and performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2490/_p
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@ARTICLE{e94-a_12_2490,
author={Kan WANG, Sheqin DONG, Yuchun MA, Yu WANG, Xianlong HONG, Jason CONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs},
year={2011},
volume={E94-A},
number={12},
pages={2490-2498},
abstract={Due to the increased power density and lower thermal conductivity, 3D ICs are faced with heat dissipation and temperature problem seriously. TSV (Through-Silicon-Via) has been shown as an effective way to help heat removal, but they introduce several issues related with cost and reliability as well. Previous researches of TSV planning didn't pay much attention to the impact of leakage power, which will bring in error on estimation of temperature, TSV number and also critical path delay. The leakage-temperature-delay dependence can potentially negate the performance improvement of 3D designs. In this paper, we analyze the impact of leakage power on TSV planning and integrate leakage-temperature-delay dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering the influence on both module delay and wire delay, is proposed to achieve the best balance among temperature, via number and performance. Experiment results show that, with leakage power and resource constraint considered, temperature and the required via number can be quite different, and the weighted TSV insertion approach with iterative process can obtain the trade-off between different factors including thermal, power consumption, via number and performance.},
keywords={},
doi={10.1587/transfun.E94.A.2490},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2490
EP - 2498
AU - Kan WANG
AU - Sheqin DONG
AU - Yuchun MA
AU - Yu WANG
AU - Xianlong HONG
AU - Jason CONG
PY - 2011
DO - 10.1587/transfun.E94.A.2490
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - Due to the increased power density and lower thermal conductivity, 3D ICs are faced with heat dissipation and temperature problem seriously. TSV (Through-Silicon-Via) has been shown as an effective way to help heat removal, but they introduce several issues related with cost and reliability as well. Previous researches of TSV planning didn't pay much attention to the impact of leakage power, which will bring in error on estimation of temperature, TSV number and also critical path delay. The leakage-temperature-delay dependence can potentially negate the performance improvement of 3D designs. In this paper, we analyze the impact of leakage power on TSV planning and integrate leakage-temperature-delay dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering the influence on both module delay and wire delay, is proposed to achieve the best balance among temperature, via number and performance. Experiment results show that, with leakage power and resource constraint considered, temperature and the required via number can be quite different, and the weighted TSV insertion approach with iterative process can obtain the trade-off between different factors including thermal, power consumption, via number and performance.
ER -
English
